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Submitted by Anonymous (not verified) on March 22, 2008 - 10:20pm.To say it over and
To say it over and over.........
If the memory control resides on the same chip , and is integrated with the CPU - then it is possible/likely that there could be problems handling a memory chip with a different way of accessing the lines. AKA AMD.
When the memory access is controlled by a separate chip on the motherboard (that is , the CPU is 'dumb' in this context), all the processor wants is data , and the delivery logic is up to the supplier. It could be construed as the Achilles heel in Intel philosophy ; but commercially works well.
Submitted by Anonymous (not verified) on March 22, 2008 - 10:20pm. To say it over and
To say it over and over.........
If the memory control resides on the same chip , and is integrated with the CPU - then it is possible/likely that there could be problems handling a memory chip with a different way of accessing the lines. AKA AMD.
When the memory access is controlled by a separate chip on the motherboard (that is , the CPU is 'dumb' in this context), all the processor wants is data , and the delivery logic is up to the supplier. It could be construed as the Achilles heel in Intel philosophy ; but commercially works well.